MIPI CSI2 Rx Core
The Foresys MIPI Core provides a fast path to integrating Image Sensors or other MIPI connected devices into a wide variety of products based on Altera devices. The MIPI CSI2 Rx core is designed to convert MIPI data from an image sensor into an Avalon Streaming Video interface.
Base Features
- Provides Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network
- Supports CSI-2 protocol for unidirectional data transfer
- Compatible with D-PHY Configured for 1 clock and 4 data lanes
- Intended for per-lane clocks rates up to 1 Gbps, depending on device speed grade
- Verifies CSI-2 header ECC field
- Verifies CSI-2 data CRC
- Transmits Avalon Streaming Video
- Optionally converts to 640×480 in RGB_888 format by simultaneously scaling and demosaicing
Example Application
This is a simple example of an Altera Max 10 FPGA being used to process image data being received by an Omnivision OV10640 MIPI camera and passing the resultant image data back out a MIPI TX interface. In this example, the FPGA has access to the video stream and can sit between a MIPI camera and the its destination.
